Evaluation of Power Delay Product for Low Power Full Adder Circuits based on GDI Logic Cell using Mentor Graphics

This paper presents high speed and low power full adder cells designed with an alternative internal logic structure and Gate Diffusion Input (GDI) logic styles and hybrid CMOS logic style that lead to have a reduced Power Delay Product (PDP). The main design objective for this adder module is not only providing low-power dissipation and high speed but also full-voltage swing. In the first design, hybrid logic style is employed. The second design is based on a different new approach which eliminates the need of XOR/XNOR gates for designing full adder cell and also by utilizing GDI, technique in its structure, it provides Ultra Low-Power and high speed digital component as well as a full voltage swing circuit. The work carried out makes a comparison against other full adders reported for low PDP in terms of speed and power consumption. All the full adders were designed with 180nm technology, and were tested using a comprehensive test bench that allowed measuring the current taken from the full adder in-outs, besides the current provided from the power supply. Post layout simulations are expected to show that the full adder’s output from its counterpart’s exhibiting an average PDP advantage of close to 80%. Key words-GDI, PDP, Full adder, Low power and Mentor graphics